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M65761FP
QM-Coder
REJ03F0234-0200 Rev.2.00 Sep 14, 2007
Description
The M65761FP is a compression and decompression LSI conforming to the high efficiency encoding system (QMCoder) in the International Standard, the JBIG/JPEG (ITU-T Recommendations T.81 and T.82) for coding still images. It also conforms to the International Standard (ITU-T Recommendation T.85) for facsimile.
Features
* 100 pin plastic molded quad flat package (fine pitch): PRQP0100JB-A (100P6S-A)
Application
* OA equipment including facsimile, copier and printer
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 1 of 33
VCC
M65761FP
13 26 68 RESET 62 CS 64 A0 39 50 75 81 87 93 100
59
69
Block Diagram
PD0
2
PD10
12
PD11
15 67 A3 63 BHE 58 WR 57 RD 71 D0 74 D3 77 D4
Host bus I/F
PD21
25
Switch Line memory
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Context table RAM Context generation QM-coder Table RAM probability estimation Typical prediction
PD22
28
PD31
37
PD0 to 11 = CX0 to 11
PD15 = PEUPE
PDRQ
38
PDAK
43
PDRD
41
80 D7 83 D8 86 D11
PDWR
42
Image data context I/F
PRDY
45
Pixel data
(= XRDY)
PTIM
47
89 D12 92 D15
(= XTIM) Context data
PXCK
48
54 DMARQ 56 DMAAK 53 INTR 55 BUS16 61 MCLK 98 TEST1 99 TEST0 1 14 27 40 51 60 70 76 82 88 94
GND
PXCKO
95
SVID
46
(= SPIX)
RVID
44
(= RPIX)
XCLK
52
XWAIT
49 96 97
Leave TOUT1 and TOUT2 open. TOUT1, 2
M65761FP
Pin Arrangement
M65761FP
PXCKO TOUT1 TOUT2 TEST0 TEST1 GND GND GND
D15
D14
D13
D12
D10
D11
VCC
VCC
VCC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 GND PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 VCC GND PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 VCC GND PD22 PD23 PD24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 D7 D6 D5 D4 GND VCC D3 D2 D1 D0 GND VCC RESET A3 A2 A1 A0 BHE CS MCLK GND VCC WR RD DMAAK BUS16 DMARQ INTR XCLK GND
SVID
XWAIT
PDRD
PDWR
PDAK
RVID
PRDY
PDRQ
PD26
PD27
PD28
PD30
PD25
PD29
PD31
PTIM
GND
PXCK
VCC
(Top view) Outline: PRQP0100JB-A (100P6S-A)
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 3 of 33
VCC
VCC
D9
D8
M65761FP
Pin Description
Classification Host bus I/F Pin Name RESET CS A0 to 3 BHE WR RD D0 to 15 DMARQ DMAAK INTR BUS16 PD0 to 31 PDRQ PDAK PDRD PDWR PRDY PTIM PXCK PXCKO SVID RVID CX0 to 11 PEUPE SPIX RPIX XCLK XWAIT XRDY XTIM MCLK TEST0, 1 VCC/GND I/O I I I I I I IO O I O I IO O I I I O I I O I O I I I O O I O I I I -- BUF S Function H/W reset signal Chip select signal Internal register address select signal High-order (D8 to 15) access signal Write strobe signal Read strobe signal I/O data signal (D0 to 7 used on 8-bit bus) Code data DMA request signal Code data DMA acknowledge signal Interrupt request signal 8-bit bus (D0 to 7) and 16-bit bus (D0 to 15) function select bus Parallel image I/O bus (PD0 to 15 used on 16-bit bus) Image data DMA request signal Image data DMA acknowledge signal Image data read strobe signal Image data write strobe signal Image data 1-line I/O start ready signal Image data 1-line transfer section signal Image data transfer clock signal Image data transfer sync clock signal Image data input signal Image data output signal Context input (CX0 can be fed back inside LSI) (= PD0 to 11) PE RAM up date enable (learning function ON/OFF) (= PD15) Coded image data input signal (= SVID) Decoded image data output signal (= RVID) Context data transfer clock signal Context data transfer wait signal Context data 1-stripe I/O start ready signal (= PRDY) Context data 1-stripe transfer section signal (= PTIM) Master clock input signal Test signal (should be connected to GND when normally used) Power supply (+5 V)/ground
Image data I/F
Parallel
Serial
Context I/F
S S 8 2 US 2 U U2 2 US US US 2 US US 4 U 2 U U U 2 4 US 2 US DS --
Others
Note:
Most of the context I/F signals are used in conjunction with the image data I/F signals. The input buffers of the input terminals (I and IO) are at TTL level. Options are as follows. (U: with pull-up resistors, D: with pull-down resistors, S: Schmitt trigger) Numbers (2, 4, 8) of the BUF column of the output terminals (O and IO) indicate current value. (one of 2, 4, or 8 mA)
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 4 of 33
M65761FP
Absolute Maximum Ratings
(Ta = -20 to +70 C unless otherwise noted)
Item Supply voltage Input voltage Output voltage Storage temperature Power dissipation Note: Symbol VCC VI VO Tstg Pd Ratings -0.3 to +7.0 -0.3 to VCC + 0.3 0 to VCC -65 to +150 1380 Unit V V V C mW Ta = 25 C, when single IC is used Conditions
All of the voltage is reference the GND terminal of the circuit. Maximum value and minimum value are expression of absolute value.
Recommend Operating Conditions
Item Supply voltage GND voltage Input voltage Operating temperature range Output capacitance (against IC) Symbol VCC GND VI Topr CL Min 4.5 -- 0 -20 -- Limits Typ 5.0 0 -- -- 50 Max 5.5 -- VCC +70 -- Unit V V V C pF Test Conditions
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 5 of 33
M65761FP
Electrical Characteristics
(Ta = -20 to +70C, VCC = 5 V 10% unless otherwise noted)
Item
"H" input voltage "L" input voltage "H" input voltage "L" input voltage Positive threshold voltage Negative threshold voltage Hysteresis width "H" output voltage "L" output voltage "H" output voltage "L" output voltage "H" output voltage "L" output voltage "H" input current "L" input current "H" output current in OFF state "L" output current in OFF state Pull up resistor PD<31:0>, PDRD, PDWR, PDAK, SVID, PTIM, PXCK, XWAIT, BUS16, DMAAK TEST1, TEST0 PD<31:0>, INTR, DMARQ, PDRQ, PRDY, RVID A<3:0>, D<15:0>, RD, WR, MCLK, BHE, RESET, CS D<15:0> XCLK, PXCKO PDRD, DMAAK, PDAK, PTIM, XWAIT, PDWR, TEST1, TEST0, RD, WR, RESET D<15:0> PD<31:0>, A<3:0>, D<15:0>, SVID, BUS16, CS, BHE MCLK, PXCK
Symbol VIH VIL VIH VIL VT+ VT- VH VOH VOL VOH VOL VOH VOL IIH IIL IOZH IOZL RU
Min 2.0 -- 4.5 -- -- 0.6 -- VCC - 0.8 -- VCC - 0.8 -- VCC - 0.8 -- -- -- -- -- 25
Limits Typ -- -- -- -- -- -- 0.2 -- -- -- -- -- -- -- -- -- -- --
Max -- 0.8 -- 0.0 2.4 -- -- -- 0.55 -- 0.55 -- 0.55 -1.0 1.0 -5.0 5.0 100
Unit V V V V V V V V V V V V V A A A A k
Test Conditions
IOH = -8 mA IOH = 8 mA IOH = -4 mA IOH = 4 mA IOH = -2 mA IOH = 2 mA VCC = 5.5 V, VI = 5.5 V VCC = 5.5 V, VI = 0 V VCC = 5.5 V, VI = 5.5 V VCC = 5.5 V, VI = 0 V VCC = 5.5 V, VI = 0 V
Pull down resistor
Dynamic consumption
RD ICCA
21 --
-- 100
100 --
k mA
VCC = 5.5 V, VI = 5 V VCC = 5.5 V, VI = VCC, GND
Note:
The value of resistor is 50 k buffer's value.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 6 of 33
M65761FP
Coding Specification
(1) Coding Algorithm * QM-Coder (JBIG standard arithmetic coding system) (2) Context (i) Built-in context mode a) Template model * 2 or 3 line 10 pixel template (see figure 1) (This agrees with the template used with the minimum resolution of JBIG) Note: The coding efficiency of the 3-line template is better than that of the 2-line template by several %. b) Adaptive template (AT) * It is possible to move up to 127 pixels on the coding line. (The position of AT given instruction by the MPU) Note: It is possible to improve the coding efficiency against the dither image by the use of AT. * It is possible to change the position of AT line by line in the middle of coding and decoding. Note: It is not possible to change the template at the time when change the position of the AT pixels. (ii) External context mode * It is possible to input any context up to 12 bits. (It is possible to interface with JBIG Progressive Coding and the Arithmatic Coding of JPEG Option Function)
X X X X X X X X X X X X X X ? X ? X X X A A
Figure 1 Template (X, A) (Top: 3-line, Bottom: 2-line)
X X X X X ? X X
A
Max 127
X X
A
X
X X
Max 127
X X
X X
X ?
X
Figure 2 Adaptive Template (A) (3) Typical Prediction * Agreement with the Typical Prediction of the lowest resolution of JBIG. The pseudo-pixel (SLNTP) is generated by the symbol LNTP which shows whether the coding/decoding process agree with the directly before line. If they agree, the line is not coding/decoding. This makes it possible to shorten the time of process and rejection of the code data. SLNTPy =! (LNTPy LNTPy - 1) (4) Deterministic Prediction * This LSI is not equipped with the Typical Prediction. However, the DP function is realized when the DP pixels are identified and eliminated by the external circuits during the external context mode. (y: line number, LNTPy = 1; LNTPy - 1 = 1)
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 7 of 33
M65761FP (5) Coding Data Format * The Stripe Data Entity (SDE) (= Stripe coded data with byte stuffing (PSCD) + end marker (SDNORM / SDRST)) Coding/decoding of one stripe portion as performed. In case of the multi-striped (construct the multi stripes) stripes are activated one at a time. (6) Marker Code * The SDE end marker is supported. (SDNORM = 02h, SDRST = 03h, ABORT = 04h) (During coding the marker code previously set in the register is outputted. During decoding, the marker code detected by requesting an interrupt to MPU when the marker is detected is read out of register.) (7) Rough Estimate of Coding and Decoding Time (T1: M65761FP as a Whole, T2: Processing Time of the Arithmetic Coding Section Alone) * The total number of clocks needed for coding and decoding 1 page (stripe) is calculates roughly using the following equations. T1 (p Lp) + (9/8 C) + ( Lp) -S ((1 - ) p Ltp - Lp) [clock] T2 (p Lp) + (9/8 C) -S ((p Ltp) - Lp)) [clock] p: Lp: Ltp: C: Number of pixels/line Number of lines/page Number of TP line/page Number of coded data bits/page 0: No TP : about 10 : about 0.3
S = 1: TP exists
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 8 of 33
M65761FP
Register Configuration
List of Registers
Address 0 Register Name System setting R/W R/W Description
1
Parameter setting
R/W
* * * * * * * * * * * * * * * * * * * * * *
2
Command
W
LSI H/W reset Coding/decoding/image data through mode selection Context selection (internal context/external context) Byte swap ON/OFF of coded/image data on host bus Bit swap ON/OFF of coded/image data on host bus Image data I/O I/F (parallel I/F, serial I/F) Image data bus bit width selection (32 bits/16 bits) Template selection (2-line/3-line template) Setting of AT pixel position (up to 127) (If 0 is set, AT becomes non-existent (default position)) Latch input/through input selection in external context input mode Context table RAM initialization command Coding (decoding, through) start/end command Start/stop command for R/W of context table RAM Selection of temporary stop and terminating end Processing status (in process/end of processing) Coded data read/write ready (ready/busy) Marker code detection (SDNORM, SDRST, ABORT, others) Interrupt request status SC counter overflow Processing mode (stop temporary/terminating end) Interrupt enable setting correspondence to each of bits positions of status register Setting the number of pixels on one line (in multiples of 16 or 32, up to 10240 pixels) lines) Setting the number of coded/decoded lines (up to 65535 lines)
2
Status
R
3 4, 5 6, 7 8, 9 A, B
Interrupt enable setting Pixel count setting Line count setting Processed line count Data write buffer
R/W R/W R/W R W
* Setting the number of lines to be coded/decoded (up to 65535 * * Buffer for writing coded data/image data/context table RAM data
from MPU into LSI (DMA transferable) (RAM address is automatically incremented each time data is written.) Buffer for reading coded data/image data/context table RAM data from LSI into MPU (DMA transferable) (RAM address is automatically incremented each time data is read).
A, B
Data read buffer
R
*
C C D
Marker code setting Marker code read Scaling
W R R/W
* Setting a terminal marker code in coding (SDNORM/SDRST) * Reading a marker code in decoding (SDNORM, SDRST, ABORT,
others)
* Reduction in coding (1/2 reduction in horizontal and vertical * * * *
directions, horizontal OR processing) Magnification during decoding (x2 lengthwise and width) Select throwing away the leading 1-byte of the coded data read when decoding Selecting the typical prediction Selection of prohibiting line memory initialization
Note:
When the 8-bit bus is used for the data read/write buffer, use address A only. Incase of the 16-bit buffer, only the word access is possible. (The byte access is not possible.)
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 9 of 33
M65761FP
Description of Registers
(1) System set up register (W/R)
(Address: 0) SYS_REG: d7 (MSB) PB d0 HR
PI
BX
BS
CX
MOD
d0 (HR):
H/W reset (0: Active, 1: Reset state) To make a H/W reset, set this bit to 1 then to 0. Reset initializes the entire LSI including the group of register and line memory. However, the context table RAM is not initialized.
d1, d2 (MOD):
This sets up the operating modes. (d2 = 0, d1 = 0: coding, d2 = 1, d1 = 0: lage data through (lage data I/F Host I/F), d2 = 0, d1 = 1: decoding, d2 = 1, d1 = 1: lage data through (Host I/F lage data I/F))
d3 (CX):
Context select (0: internal context, 1: Image data through) Note: The internal context should be selected when the image data through mode is used. When initializing or processing R/W of the context table RAM and coding/decoding. This bit must be set the same. (Because RAM configuration changes depending on internal/external modes.) Select data bit swap of the host bus. (0: MSB (d7) first, 1: LSB (d0) first) Select data byte swap of the host bus. (0: Lower byte (A) first, 1: Upper byte (B) first) Note: BX is valid only when the host bus is 16 bits. (BUS16 = HIGH)
d4 (BS): d5 (BX):
Table 1 The Coed Data and Image Data Lineup on the Host Bus
Bus Width BUS16 1 16-bit Swap BX 0 0 1 1 -- -- BS 0 1 0 1 0 1 d15 b8 b15 b0 b7 Upper Address (B) ***** ***** ***** ***** ***** -- -- d8 b15 b8 b7 b0 d7 b0 b7 b8 b15 b0 b7 Lower Address (A) ***** ***** ***** ***** ***** ***** ***** d0 b7 b0 b15 b8 b7 b0
0 8-bit Note:
b0 is the first coded data on the time series/the left-hand side image data on the screen. b15 is the last coded data on the time series/the right-hand image data on the screen.
b6 (PI): b7 (PB):
Selects the image data I/O I/F (0: Serial I/F, 1: Parallel I/F) Selects the bit width of the image data bus (0: 32-bit bus (PD0 to 31), 1: 16-bit bus (PD0 to 15))
Table 2 The Image Data Lineup on the Image Data Parallel Bus
Bit Width PB = 0 PB = 1 Note: PD31 p0 ***** ***** -- PD16 p15 PD15 p16 p0 ***** ***** ***** PD0 p31 p15
p0 is the image data on the left-hand on the screen. p31 is the image data on the right-hand on the screen.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 10 of 33
M65761FP (2) Parameter setup register (WR) 1) External context mode
(Address: 1) PARA_REG: d7 C0 LC 0 d4 0 d0
d6 (LC):
Condition of taking in the input from the external context are selected. (0: through output, 1: latch input) When this bit is set to 1, the CX0 to CX11 of the context input is latched once using the transfer clock. ("XCLK")
d7 (C0):
When this bit is set to 1, CX0 is selected. (0: CX0 external input, 1: CX0 internal feedback)
2) Internal context mode
(Address: 1) PARA_REG: d7 AT d6 d5 TM d4 AT d0
d0 to 4 (AT<0> to AT<4>): d5 (TM): d6, d7 (AT<5>, AT<6>):
Example: 3-line template, AT = 4: 2-line template, AT = 48:
AT pixel position lower 5 bits. (see figure 2) Template select (0: 3-line template, 1: 2-line template) AT pixel position upper 2 bits (the 6th and 7th bits)
d7 0 d7 0 1 1 0 0 d4 1 0 0 0 0 d4 0 0 1 0 0 d0 d0
Note: The AT pixel position at time of the internal context mode is set up by using all the AT<6:0> (0 to 127). When the default position (when the AT pixels are not used) is used, AT is set to 0. When the 2-line template is used, AT should not be set to 1 to 4. In case of the 3-line template, AT = 1 to 2 is not allowed. (3) Command register (W)
(Address: 2) CMD_REG: d7 0 d3 JP d0 IC
RC
JC
d0 (IC):
This command starts initialization of context table RAM (1: start initialization) When this bit goes 1, the context table RAM initialization starts. This bit returns to 0 automatically when the initialization is completed.
d1 (JC):
Processing (coding/decoding/through) start/end command (1: start processing, 0: end processing) When this bit goes 1, processing (coding/decoding/through) starts. This bit returns to 0 automatically when processing of the number of set lines is finished during the selection of end of termination. And if this JC bit is made 0 and inputting the image data is stopped during the coding process, the coding is stopped (flushed) even if the set lines are not filled. Moreover, if this bit made 0 during decoding and no more coded data is coming in, it is assumed that the "00" of the coded data came in and the preset lines have been processed. However, in case of the multi-striped coding, processing should not end by making this bit "0" except in case of last stripe.
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M65761FP d2 (RC): This command starts and stops R/W of context table RAM. (1: R/W start, 0: R/W end) The context table RAM is read out or written in by making this bit to "1". When reading/writing is finished, this bit must have "0" on it. d3 (JP): This selected temporary stop and the end of termination of coding/decoding/through processing. (1: Temporary stop selected, 0: End of processing selected) When the process start command d1 (JC) is issued by making this JP bit to 1, the processing stops temporarily when the set number of lines have been processed. Then, if the process start command d1 (JC) is issued, processing restarts. (See " Sequence of Setting Up Registers " (3)) (4) Status register (R)
(Address: 2) STAT_REG: d7 0 d5 PS d0 JS
SC
IS
MS
DS
d0 (JS):
This register indicates the status of processing in initialization, coding, decoding and through. (0: Processing in progress (being initialized), 1: End of processing) This JS bit goes to "1" when the initialization is completed as RAM initialization command is issued. (IC = 1) This JS bit goes to "1" when all coded data has been read out during coding in case when the process start command of the processing end is issued. (JC = 1, JP = 0) This JS bit goes to "1" when reading all the image data has been completed during the image data through and decoding. Moreover, this JS bit stays "0" even when the set number of lines have been processed when the command to start processing the process which has been stopped temporarily has been issued (JC = 1, JP = 1). (However, interrupts are issued during the temporary stops.)
d1 (DS):
This is used for read and write ready of coded data. (In case of the through mode, this is used for the image data.) (1: Ready, 0: Reading no possible) It is possible to do R/W of data by the way of the data write/read buffer when this bit is 1.
d2 (MS):
This detects the marker code during decoding. (0: not detected, 1: detected) This bit goes to "1" if any marker is detected during decoding.
d3 (IS): d4 (SC):
This indicates the status of the interrupt request. (0: No request, 1: Request exists) This shows the SC count over error during coding. (0: Normal, 1: There is a SC counter overflow) Note: The SC counter counts the "FF" data bytes which occur during coding. Coding continues even when the SC counter overflows, this means correct coding data will not be outputted. (Coding error)
d5 (PS):
Processing modes (Stopped temporary/End of trailer) (1: Process temporarily stopped, 0: End of processing) This PS bit corresponds to the temporary stop and end of processing of d3 bit (JP) processing of the command register.
(5) Interrupt enable register (W/R)
(Address: 3) IENB_REG d7 MP d3 SE d0 JE
0
ME
DE
d0 (JE):
Temporary stop/end of trailer interrupt of initialization/coding/decoding/through. (0: interrupt mask, 1: interrupt enable)
d1 (DE):
Coded data (image data) read out/write in ready interrupt. (0: interrupt mask, 1: interrupt enable)
d2 (ME):
Marker code detection interrupt during decoding. (0: interrupt mask, 1: interrupt enable)
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M65761FP d3 (SE): SC count over error interrupt during coding. (0: interrupt mask, 1: interrupt enable) This bit sets to 1 beforehand, it occurs the interruption when the SC counter is overflow during coding. Processing of coding continues, but the correct coded data is not output. Note: Bits, d0 to d3, are for interrupt enable of bits d0 to d2 and d4 of the status register. The interrupt request signal (INTR) is asserted when any one of the status bit set in the interrupt enable (D0 (JE) generates interrupts even during the temporary stop), the status goes to "0" due to H/W reset or the INTR signal is negated when the interrupt mask causes factors for interrupt to be lost. Moreover, the status register will not be cleared by the generation of interrupts or the R/W of the interrupt enable register. This specified the marker code detection time halt. (0: continue/restart, 1: temporary halt) Decoding will stop temporarily when the marker code is detected if this MP bit is preset to "1" during decoding. (It occurs interruption when the marker code is detected, if the ME bit preset to "1".) If decoding is not completed during the temporary halt, it is possible to reset the line number setup register. Next, if this MP bit is set to "0", decoding is restarted. (Decoding continues to the line number set.) (6) Register used to set the number of pixels (W/R)
(Address: 4) PEL_REG_L: (Address: 5) PEL_REG_H: d7 PEL_L d7 0 d5 PEL_H d0 d0
d7 (MP):
d0 to 7 (PEL_L): d0 to 5 (PEL_H):
Number of pixels/line is set (Lower byte) Number of pixels/line is set (Upper byte) It is possible to set up 8192 pixels maximum when 3-line template is used. It is used to set up 10240 pixels maximum when 2-line template is used. The number of pixels actually coded (or decoded) should be set when reducing (or expanding). When the image bus uses 16 bits (or 32 bits) in parallel I/F, multiples of 16 (or 32) should be set. In case of serial I/F, multiples of 8 should be used.
(7) Line number setting register (W/R)
(Address: 6) LSET_REG_L: (Address: 7) LSET_REG_H: d7 LSET_L LSET_H d0
d0 to 7 (LSET_L):
This sets the number of lines to be processed. (Lower bytes) (1 to 65535, 0 line not used)
d0 to 7 (LSET_H):
This sets the number of lines to be processed. (Upper bytes) When reducing (magnification) the actual number of lines to be coded (decoded) should be set. The number of lines (relative number of lines) from the process start command to be issued from now the immediately following temporary stop/end of trailer should be set. This register should be set to the value specified before the process star command is issued. Moreover, this register can be rewritten during processing as long as the following conditions are met: * If the maximum value, (65535), is set before the process start command is issued, it can be reset once during processing. * If a value other than maximum value (65535) is set before the process start command is issued and if resetting becomes necessary during processing, the maximum value (65535) has to be reset once and desired value should the reset.
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M65761FP (8) Number of lines to be processed specified (R)
(Address: 8) LIN_REG_L: (Address: 9) LIN_REG_H: d7 LINE_L LINE_H d0
d0 to 7 (LINE_L): d0 to 7 (LINE_H):
The number of lines actually processed is read out (Lower bytes) (0 to 65535) The number of lines actually processed is read out (Upper bytes) When the number of lines processed number of lines set, coding/decoding/through stops temporarily/end of processing. Note: The number of lines to be processed by this processing is cleared to 0 by the issuance of process start command.
(9) Data write in buffer (W) (See note 1)
(Address: A) DWR_BUF_L: (Address: B) DWR_BUF_H: d7 DWR_L DWR_H d0
d0 to 7 (DWR_L): d0 to 7 (DWR_H):
This writes in the coded data/image data/context table RAM data (Lower bytes) This writes in the coded data/image data/context table RAM data (Upper bytes)
(10) Data read out buffer (R) (See note 1)
(Address: A) DRD_BUF_L: (Address: B) DRD_BUF_H: d7 DRD_L DRD_H d0
d0 to 7 (DRD_L): d0 to 7 (DRD_H):
This read out the coded data/image data/context table RAM data. (Lower bytes) This read out the coded data/image data/context table RAM data. (Upper bytes)
Note: 1. Address A is used with 8-bit bus. In case of the 16-bit bus, only the word access is possible. (Not byte access) If the number of coded data bytes is an odd number during coding, an one byte pad ("00") is attached after the end marker is issued in order to use it as a word boundary. See table 1 for the bit arrangement used during the coded data/image data. In case of the context table RAM data, only the lower byte becomes valid data regardless of the bus width of the host bus (BUS16). Table 3 Context Data Lineup
Host I/F Bus Width 8-bit 16-bit Note: Upper Address (B) d15 ***** -- --- d8 d7 mps mps Lower Address (A) d6 s6 s6 ***** ***** ***** d0 s0 s0
mps: Superior symbol MPS (expected value 0/1) s6 to 0: Status number ST (0 to 112)
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M65761FP (11) Marker code set up register (W)
(Address: C) MSET_REG: d7 MSET d0
d0 to 7 (MSET):
The end marker code used during coding is set. (SDNORM = 02h, SDRST = 03h) The byte set to this register is outputted as the end marker during coding.
(12) Marker code read out register (R)
(Address: C) MDET_REG: d7 MDET d0
d0 to 7 (MDET):
The marker codes detected during decoding are read out. (SDNORM = 02h, SDRST = 03h, ABORT = 04h, etc.) The marker codes detected during decoding read out as is.
(13) This register sets up various functions (W/R)
(Address: D) CONV_REG: d7 TP LI OB HO HR VR HE VE d0
d0 (VE): d1 (HE):
Selects expansion in lengthwise direction during decoding. (0: Equal dimension, 1: 2 expansion) Selects expansion sideways during decoding. (0: Equal dimension, 1: 2 expansion) d0 and d1 are possible only during decoding.
d2 (VR): d3 (HR):
Selects reduction in lengthwise direction during coding. (0: Equal dimension, 1: 1/2 reduction) Selects sideways reduction during coding. (0: Equal dimension, 1: 1/2 reduction) d2 and d3 are possible only during coding.
d4 (HO):
Selects thinning in sideways direction during coding. (0: Simple thinning, 1: OR processing) This reduction is valid only during coding. Notes: 1. This lengthwise 1/2 reduction during coding is used for the simple thinning. (Odd lines are skipped) 2. The number of lines for image data to be inputs when VR = 1 for coding must be twice the value set by the register which sets the number of lines. 3. The number of lines for image data to be outputs when VE = 1 for decoding must be twice the value set by the register which sets the number of lines. This selects if the leading 1 byte is discarded during decoding. (0: Normal processing (No discarding), 1: The leading 1 byte is discarded) If a command to start processing the first the stripe decoding is issued during decoding while OB is set to "1", the leading 1 byte of the input data is discarded. (Not used for decoding) If OB = 0, the one of byte discarding process is not used. (Normal decoding used) For example, this function is used by the Host 16 bits bus when the leading 1 byte of the input data word is an invalid data. Note: Selecting this function is valid in case of the host 8 bits bus and the external context mode also.
d5 (OB):
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 15 of 33
M65761FP d6 (LI): Line memory initialization is prohibited. (0: Initialization specified, 1: Initialization prohibited) When a command to start processing coding/decoding of the first stripe is issued, if L1 = 1, the initialization of the internal line memory is prohibited. (The last image data of the immediately prior coding/decoding left in the line memory is used as the leading reference line data of the next coding/decoding.) When LI = 0, the internal line memory is initialized. (All white (0) data is used as the leading reference line data of the next coding/decoding.) In case when the previous stripe ended with SDNORM during coding/decoding of multi-stripe by setting this bit in the initialization prohibit (1). Note: Even when LI = 1 is set, this LI bit is cleared (0) and the internal line memory will be initialized the same line due to the fact that the H/W reset is written into the external reset terminal or the system set up register. d7 (TP): This selects the typical prediction when coding and decoding. (0: Typical prediction OFF, 1: Typical prediction ON)
Initialization of Register Each register is initialized as shown in the table below by writing H/W reset to the external RESET terminals or the system set up registers. Table 4 Initialization Values for Registers
Registers System set up Parameter set up Command Status Interrupt enable Number of pixels set up Set up number of lines Number of lines processed Data buffer Marker code set up Marker code read out Various functions set up Note: 00h 00h 00h 00h 00h 00h 00h 00h Indefinite 00h 00h 00h
Note
Initialization Values
When writing H/W RESET into the System Setup Register, the value written into is set up in the System Setup Register.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 16 of 33
M65761FP
Sequence of Setting Up Registers
(1) Initialization sequence of the internal line memory and context table RAM This sequence starts with the initialization set up (see note) of internal line memory by the H/W RESET. It is followed by the initialization of the context table RAM. (Clear)
1
H/W Reset Context mode set up
d7
d0 0
0
SYS_REG: SYS_REG:
0
0
0
0
0
0
0
C
0
0
0
0
1
0
; H/W reset bit ON ; H/W reset bit OFF ; C = Context mode set up
The ON time for H/W RESET bit (The time from d0 = "1" is written in to the time when d0 = "0" is written in) should be 100 ns more.
Context table RAM Initialization command issued
CMD_REG:
0
0
0
0
0
0
0
1
; Context table initialized
Interrupt enable set up
IENB_REG:
0
0
0
0
0
0
0
1
; Process end interrupt enable
[During this time, the context table RAM is initialized.] The number of clocks needed for initialization is as follows, When the internal text mode is used. 1024 + [clocks] When the external text mode is used. 4096 + [clocks]
(Interrupt generation)
d7 d0 0 0
0
Set up interrupt enable
IENB_REG:
0
0
0
0
1
; Interrupt disable
Status register read out (Check if processing finished)
STAT_REG:
-
-
-
-
-
-
-
j
; j = End of processing
j=1?
Y End of initialization command
N
(Error)
CMD_REG:
0
0
0
0
0
0
0
0
; End of initialization
to 2
Note:
Initialization of the line memory by H/W RESET is provided for the start of coding and decoding by preparing the all white (0) data as a reference line. At the same time, it initializes the LNTP bit to LNTP = 1 for the Typical Prediction.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 17 of 33
M65761FP (2) Coding/decoding of stripes (no change in the AT pixel position)/image data through processing sequence
2
d7 d0 p x
s
System set up (LSI mode set up)
SYS_REG:
b
Cmm
0
Parameter set up (Template, context)
PARA_REG: PEL_REG_L: PEL_REG_H: LSET_REG_L: LSET_REG_H: MSET_REG:
c/a l/a
t
a
a
a
a
a
; mm = Operating mode (Coding/decoding) ; C = Context selection (Internal/external) ; s, x = Bit, byte swap ; p, b = Image data I/F, bit width ; aa,aaaaa = AT pixel position ; t = Template selection ; l = Conditions to take in external context ; c = External context CX0 selects ; pel_l, pel_h = Number of pixels per line
pel_l
0 0
pel_h
Set up number of pixels
Set up number of lines
Set up marker code (Note: coding only)
lset_l
lset_h
; lset_l, lset_h = Number of lines processed ; mset = marker code byte set up (SDNORM = 02h, SDRST = 03h) ; Ve, He = Select expansion during decoding ; Vr, Hr, Ho = Select reduction during coding ; Ob = Select discarding leading 1 byte during decoding ; Tp = ON/OFF of typical prediction function ; Li = Select prohibiting initialization of line memory ; End of trailer processing (Coding/decoding/through) start command ; Processing end interrupt enable
mset
Set up functions
CONV_REG:
Tp Li Ob Ho Hr Vr He Ve
Note: Set Li to "0" when it is the leading stripe of single or multi stripe.
Process start command (Coding/decoding/through)
CMD_REG:
0
0
0
0
0
0
1
0
Set up interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
When the external context mode is used, it is not necessary to set the position of AT pixels, number of pixels, number of lines, and expansion, reduction/typical prediction/line memory initialization selection. (They will be invalid) [Coding and decoding are performed during this time]---I/O of image data and code data is performed. (Coding and decoding of stripe is performed.) (Interrupt is generated)
d7
d0 0 0
0
Interrupt disable is set up
IENB_REG:
0
0
0
0
0
; Interrupt disable ; j = End of processing ; m = Marker detection ; s = SC counter overflow
Status register is read out (Check end of processing)
N
STAT_REG:
-
-
-
s
-
rn
-
j
j=1?
(Error)
Y
N (Coded) Decoded ? Y
(Decoded)
N (Marker not yet detected)
s=0? Y
N (SC counter overflow)
(Error)
m=1? Y
(Error) (Marker detected)
End
Marker code read out Note: only for decoding
MDET_REG:
mdet
; mdet = marker code read out
End
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 18 of 33
M65761FP (3) Processing sequence of coding/decoding of stripes (internal context mode and AT pixel position may change)
2
System set up (LSI mode set up)
Parameter set up (Template, AT pixel position)
d7 d0 p x
s
SYS_REG:
b
Cmm
0
PARA_REG: PEL_REG_L: PEL_REG_H: LSET_REG_L: LSET_REG_H: MSET_REG:
a
a
t
a
a
a
a
a
; mm = Operating mode (Coding/decoding) ; C = 0 Internal context selected ; s, x = Bit and byte swap ; p, b = Image data I/F, bit width ; aa,aaaaa = AT pixel position ; t = Template selection ; pel_l, pel_h = Number of pixels per 1 line ; lset_l, lset_h = Number of lines process
Note: The number of lines up to the point where AT pixel position is changed is set.
Set up number of pixels
pel_l
0 0
pel_h
Set up number of lines
lset_l
lset_h
Set up marker code (Note: coding only)
mset
Set up various functions
CONV_REG:
Tp Li Ob Ho Hr Vr He Ve
Note: Set Li to "0" when the leading stripe of single or multi stripe is used.
Process start command (Stop processing temporarily)
; mset = Marker code byte set up (SDNORM = 02h, SDRST = 03h) ; Ve, He = Expansion selection for decoding ; Vr, Hr, Ho = Select reduction during coding ; Ob = Select discarding leading 1 byte when coding ; Tp = ON/OFF of typical prediction function ; Li = Select prohibiting initialization of line memory Note
CMD_REG:
0
0
0
0
1
0
1
0
; Stop processing temporarily (Coding/decoding)
Set up interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Processing stop interrupt enable
[Coding/decoding go on during this time]---I/O of the first image data and code data take place.
Note: During the first processing, if it is coding, (the number of lines of the input image data) = (the value set in the register which sets the number of lines) + 1 During decoding, (number of lines of the output image data) = (the value set in the register which sets the number of lines) - 1
(Interrupt is generated)
d7 d0 0 0
0
Interrupt disable is set up
IENB_REG:
0
0
0
0
0
; Interrupt disable ; Status check ; j = 0, p = 1, temporary check
Status register is read out
STAT_REG:
-
-
p
-
-
-
-
j
Set up the last AT
Last set up
Go to 3
Middle of set up
Set up AT pixel position
PARA_REG:
a' a'
t
a' a' a' a' a'
; AT pixel change set up (a'a', a'a'a'a'a')
Note: Template not to be changed
; lset_l, lset_h = Number of lines process
Set up number of lines
LSET_REG_L: LSET_REG_H:
lset_l
lset_h
Note: Set up the number of lines to be processed from the time processing restarted to the position where next the next AT pixel is changed.
to Next page
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 19 of 33
M65761FP
(To previous page)
This routine is repeated the (AT move - 1) times
Process start command (Temporary stop command)
CMD_REG:
0
0
0
0
1
0
1
0
; Command to restart processing which stopped temporarily (Coding/decoding)
Set up interrupt enable
IENB_REG:
0
0
0
0
0
0
0
1
; Processing end interrupt enable
[Coding and decoding are performed during this time]---I/O of image data and code data is performed.
Note: During the above processing the following is true. During coding, (The number of lines of the input image data) = (Number of lines set in the line number setting register) During decoding, (Number of lines of the output image data) = (Number of lines set in the line number setting register)
(Interrupt is generated)
d7 d0 0 0
0
Interrupt disable is set up
IENB_REG:
0
0
0
0
0
; Interrupt disable
Status register is read out (Check end of processing)
STAT_REG:
-
-
-
s
-
m
-
j
; j = End of processing ; m = Marker detection ; s = SC counter overflow
N
j=1?
(Error)
Y
N (Coded) Decoded ? Y
(Decoded)
N (Marker not yet detected)
s=0? Y
N (SC counter overflow)
(Error)
m=1?
End
(Error)
Y
(Marker detected)
Marker code read out Note: only for decoding
MDET_REG:
mdet
; mdet = Marker code read out
End
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 20 of 33
M65761FP (4) Read out/write in sequence of context table RAM This sequence dies R/W of context table RAM.
d7 d0 - - - C - - 0
Set context mode
SYS_REG: CMD_REG:
-
; H/W reset bit OFF ; C = Context mode set ; Start of R/W context table RAM
Start command for R/W of RAM
0
0
0
0
0
1
0
0
[Reading (writing) of context table RAM continues during this time.] RAM data is outputted (inputted) by way of data read (write) buffer. The RAM address is automatically incremented every time 1 byte is read out (write in). Note: It is not possible to mix reading and writing.
End of R/W command of RAM
CMD_REG:
0
0
0
0
0
0
0
0
; End of R/W command of RAM This does not end automatically. Be sure to write the end of R/W command.
Note: The assignment of address for context table RAM is as follows Internal context mode: Address 0 to 1023 of (LSB: 0, MSB: 9) as shown below. External context mode: Address 0 to 4095 of (LSB: CX0, MSB: CS11)
876 54329 10?
3-line template
854329 7610?
2-line template
(AT pixel is MSB: 9)
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 21 of 33
M65761FP (5) Overall sequence of multi-stripe coding/decoding The image whose 1 page is composed of multiple stripes must perform (2) or (3) by stripes after the initialization of (1).
multi-stripe coding/decoding
Internal memory & context table RAM are initialized. (1) processing
Coding/decoding of 1st stripe (2) or (3) processing
All stripes process ended? N
This routine is repeated (Number of stripes - 1)
Y
End of page
Is the previous stripe SDNORM? Y (SDNORM)
N (SDRST)
Initialization of internal line memory and context table RAM (1) processing
Stripe coding/decoding (Line memory initialization prohibited: Li = 1, AT pixel = the value of previous stripe [(2) or (3) is processed]
stripe coding/decoding process (line memory initialization is specified by Li = 0, AT pixel = default position (0) [(2) or (3) is processed]
Notes:
1. When 16-bit bus is used for the host-bus during coding, in order to use the word boundary, the pad byte ("00") 1 byte long tends to follow behind the end marker code of each stripe. This must be eliminated externally. 2. When starting decoding of each stripe (during decoding), inputting must start from the leading coded data of SDE (stripe data entity). If necessary, the leading 1 byte is discarded. (In case when the leading portion of coded data of the next stripe is already inputted in LSI (FIFO) or when it is not lined up with the lead boundary during decoding of each stripe ends, external management is needed. 3. Management of marker codes (AT MOVE, NEWLEN, etc.) processing (insertion at the time of coding and detection/removing at the time of decoding) should be done externally.
Description If the end marker of the stripe one before is SDNORM, do not initialize the line memory nor the context table RAM. The AT pixel position will use the last value of the previous stripe and starts processing next stripe. In case of SDRST, initialization takes place first and then the AT pixel position is returned to the default position. Then the processing of the next stripe begins.
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 22 of 33
M65761FP
Timing Characteristics 1
(Ta = -20 to +70C, VCC = 5 V 10% unless otherwise noted) 1) Host Bus I/F
Item D0 to 15 output define time for RD assert Symbol tPZL (RD-D0 to 15) tPZH (RD-D0 to 15) tPLZ (RD-D0 to 15) tPHZ (RD-D0 to 15) tPHL (DMAAK-DMARQ) Min 0 0 0 0 -- Limits Typ -- -- -- -- -- Max 30 30 30 30 20 Unit ns ns ns ns ns Test Circuit 1 Test Conditions CL = 50 pF
D0 to 15 output hold time for RD assert
DMARQ negate time for DMAAK assert
2) Image Data I/F
Limits Item PRDY negate time for PTIM assert RVID output define time for the fall of PXCK PXCKO delay time for PXCK Symbol tPLH (PTIM-PRDY) tPHL (PXCK-RVID) tPLH (PXCK-RVID) tPHL (PXCK-PXCKO) tPLH (PXCK-PXCKO) tPHL (PXCKO-RVID) tPLH (PXCKO-RVID) tPLH (PTIM-RVID) tPHL (PDAK-PDRQ) tPZL (PDRD-PD0 to 31) tPZH (PDRD-PD0 to 31) tPLZ (PDRD-PD0 to 31) tPHZ (PDRD-PD0 to 31) Min -- -- -- -- -- -- -- 0 -- 0 0 0 0 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 30 25 25 15 15 10 10 -- 20 30 30 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Circuit 1 Test Conditions CL = 50 pF
RVID output define time for the fall of PXCKO RVID negate time for PTIM negate PDRQ negate time for PDAK assert PD0 to 31 output define time for PDRD assert PD0 to 31 hold time for PDRD negate
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 23 of 33
M65761FP 3) Context I/F
Limits Item XRDY negate time for XTIM assert time RPIX output define time for the fall of XCLK XCLK delay time for MCLK Symbol tPLH (XTIM-XRDY) tPLH (XCLK-RPIX) tPHL (XCLK-RPIX) tPLH (MCLK-XCLK) tPHL (MCLK-XCLK) Min -- 0 0 -- -- Typ -- -- -- -- -- Max 30 30 30 30 30 Unit ns ns ns ns ns Test Circuit 1 Test Conditions CL = 50 pF
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 24 of 33
M65761FP
Timing Characteristics 2
(Ta = -20 to +70C, VCC = 5 V 10% unless otherwise noted) 1) Host Bus I/F
Item RESET assert time CS set up time for RD asset CS hold time for RD negate A0 to 3 set up time for RD assert BHE set up time for RD asset RD asset time A0 to 3 hold time for RD negate BHE hold time for RD negate CS set up time for WR assert CS hold time for WR negate A0 to 3 set up time for WR assert BHE set up time for WR assert WR assert time A0 to 3 hold time for WR negate BHE hold time for WR negate D0 to 15 input set up time for WR negate D0 to 15 input hold time for WR negate DMAAK set up time for RD assert DMAAK hold time for RD negate DMAAK set up time for WR assert DMAAK hold time for WR negate Symbol tw (RESET) tsu (RD-CS) th (RD-CS) tsu (RD-A0 to 3) tsu (RD-BHE) tw (RD) th (RD-A0 to 3) th (RD-BHE) tsu (WR-CS) th (WR-CS) tsu (WR-A0 to 3) tsu (WR-BHE) tw (WR) th (WR-A0 to 3) th (WR-BHE) tSU (WR-D0 to 15) th (WR-D0 to 15) tsu (RD-DMAAK) th (RD-DMAAK) tsu (WR-DMAAK) th (WR-DMAAK) Min 100 20 20 20 20 30 20 20 20 20 20 20 30 20 20 20 20 20 20 20 20 Limits Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Circuit 1 Test Conditions CL = 50 pF
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 25 of 33
M65761FP 2) Image Data I/F
Limits Item MCLK period (Mx) when used image data I/F MCLK high level time (Mh) when used image data I/F MCLK low level time (Ml) when used image data I/F MCLK rising time when used image data I/F MCLK falling time when used image data I/F PTIM set up time for the fall of PXCK PTIM hold time for the rise of PXCK PXCK high time PXCK low time PXCK period SVID set up time for the fall of PXCK SVID hold time for the rise of PXCK PDAK set up time for PDRD assert PDAK hold time for PDRD negate PDRD assert time PDAK set up time for PDWR assert PDAK hold time for PDWR negate PDWR assert time PD0 to 31 input set up time for PDWR negate PD0 to 31 input hold time for PDWR negate Symbol tci (MCLK) Min 50 Typ -- Max -- Unit ns Test Circuit 1 Test Conditions CL = 50 pF
twi+ (MCLK)
20
--
--
ns
twi- (MCLK)
20
--
--
ns
tri (MCLK)
--
--
20
ns
tfi (MCLK)
--
--
20
ns
tsu (PXCK-PTIM) th (PXCK-PTIM) tw+ (PXCK) tw- (PXCK) tc (PXCK) tsu (PXCK-SVID) th (PXCK-SVID) tsu (PDRD-PDAK) th (PDRD-PDAK) tw (PDRD) tsu (PDWR-PDAK) th (PDWR-PDAK) tw (PDWR) tsu (PDWR-PD0 to 31)
20 20 20 20 50 10 10 20 20 30 20 20 20 20
-- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
th (PDWR-PD0 to 31)
20
--
--
ns
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 26 of 33
M65761FP 3) Context I/F
Limits Item MCLK period (Mx) when used context I/F MCLK high level time (Mh) when used context I/F MCLK low level time (Ml) when used context I/F MCLK rising time when used context I/F MCLK falling time when used context I/F XTIM assert time for the rise of MCLK XTIM negate time for the rise of XCLK XCLK high time XCLK low time XCLK period XWAIT negate time for the rise of XCLK CX0 to 11 set up time for the rise of XCLK PEUPE set up time for the rise of XCLK SPIX set up time for the rise of XCLK CX0 to 11 hold time for the rise of XCLK PEUPE hold time for the rise of XCLK SPIX hold time for the rise of XCLK CX0 to 11 set up time for the rise of XCLK SPIX set up time for the rise of XCLK CX0 to 11 hold time for the rise of XCLK SPIX hold time for the rise of XCLK PEUPE input define time for the rise of XCLK Symbol tcc (MCLK) twc+ (MCLK) Min 100 40 Typ -- -- Max -- -- Unit ns ns Test Circuit 1 Test Conditions CL = 50 pF
twc- (MCLK)
40
--
--
ns
trc (MCLK) tfc (MCLK) tsu (MCLK-XTIM) th (XCLK-XTIM) tw+ (XCLK) tw- (XCLK) tc (XCLK) th (XCLK-XWAIT) tsul (XCLK-CX0 to 11) tsul (XCLK-PEUPE) tsul (XCLK-SPIX) thl (XCLK-CX0 to 11) thl (XCLK-PEUPE) thl (XCLK-SPIX) tsut (XCLK-CX0 to 11) tsut (XCLK-SPIX) tht (XCLK-CX0 to 11) tht (XCLK-SPIX) tk (XCLK-PEUPE)
-- -- 20 -- -- -- -- 0 20 20 20 20 20 20 70 70 20 20 --
-- -- -- -- Mh Ml Mx -- -- -- -- -- -- -- -- -- -- -- --
20 20 -- 20 -- -- -- 10 -- -- -- -- -- -- -- -- -- -- 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 27 of 33
M65761FP
Test Circuit
1 Input VCC Output VCC
RL = 1 k
SW1 PG DUT SW2
50
GND
CL RL = 1 k
Item tPLH, tPHL tPLZ tPHZ tPZL tPZH
SW1 Open Close Open Close Open
SW2 Open Open Close Open Close
(1) Characteristic of pulse generation (PG) (10% to 90%) tr = 3 ns, tf = 3 ns (2) Capacitance CL includes stray wiring capacitance and probe input capacitance.
Master Clock
tci (MCLK) tcc (MCLK) twi+ (MCLK) twc+ (MCLK) twi- (MCLK) twc- (MCLK)
tfi (MCLK) tfc (MCLK)
tri (MCLK) trc (MCLK)
90%
90%
MCLK
10% 10%
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 28 of 33
M65761FP
Host Bus I/F
(1) MPU Access
RESET
tw (RESET)
CS tsu (RD-CS)
th (RD-CS)
tsu (WR-CS)
th (WR-CS)
A0 to 3 BHE tsu (RD-A0 to 3) tsu (RD-BHE) RD tw (RD) th (RD-A0 to 3) th (RD-BHE) th (WR-A0 to 3) th (WR-BHE)
tsu (WR-A0 to 3) tsu (WR-BHE)
tw (WR)
WR
tPZL (RD-D0 to 15)
tPLZ (RD-D0 to 15)
D0 to 15
50% 10% tPZH (RD-D0 to 15) 50% tPHZ (RD-D0 to 15)
tsu (WR-D0 to 15)
th (WR-D0 to 15)
D0 to 15
90%
Input
(2) DMA Access
DMARQ
50%
tPHL (DMAAK-DMARQ) DMAAK
tsu (RD-DMAAK)
tw (RD)
th (RD-DMAAK)
RD tsu (WR-DMAAK) WR tw (WR) th (WR-DMAAK)
tPZL (RD-D0 to 15) 50%
tPLZ (RD-D0 to 15) tsu (WR-D0 to 15)
D0 to 15
10% tPZH (RD-D0 to 15) 50% tPHZ (RD-D0 to 15)
th (WR-D0 to 15)
D0 to 15
90%
Input
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 29 of 33
M65761FP
Image Data I/F
(1) Serial Image Data I/F
PRDY
50% tPLH (PTIM-PRDY)
PTIM tc (PXCK) tsu (PXCK-PTIM)
tw- (PXCK)
tw+ (PXCK)
th (PXCK-PTIM)
PXCK tPHL (PXCK-RXCKO) tPLH (PXCK-RXCKO) tPLH (PXCKO-RVID) PXCKO
tPHL (PXCKO-RVID) tPHL (PXCK-RVID) PVID 50%
tPLH (PXCK-RVID)
tPLH (PTIM-RVID)
50%
50%
tsu (PXCK-SVID) SVID
th (PXCK-SVID)
(2) Parallel Image Data
PDRQ
50% tPHL (PDAK-PDRQ)
PDAK tsu (PDRD-PDAK) th (PDRD-PDAK)
tw (PDRD)
PDRD tsu (PDWR-PDAK) PDWR tPZL (PDRD-PD0 to 31) 50% 10% tPZH (PDRD-PD0 to 31) 50% tPHZ (PDRD-PD0 to 31) Input tPLZ (PDRD-PD0 to 31) tsu (PDWR-PD0 to 31) th (PDWR-PD0 to 31) tw (PDWR) th (PDWR-PDAK)
PD0 to 31
90%
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 30 of 33
M65761FP
Context I/F
(1) Latch Input Mode
XRDY
50% tPLH (XTIM-XRDY)
XTIM
tsu (MCLK-XTIM)
MCLK
tPHL (MCLK-XCLK)
tPLH (MCLK-XCLK)
XWAIT tc (XCLK) tw- (XCLK) XCLK tw+ (XCLK) th (XCLK-XWAIT) th (XCLK-XTIM)
tsul (XCLK-CX0 to 11) tsul (XCLK-PEUPE) tsul (XCLK-SPIX) CX0 to 11 PEUPE SPIX
thl (XCLK-CX0 to 11) thl (XCLK-PEUPE) thl (XCLK-SPIX)
tPHL (XCLK-SPIX)
tPLH (XCLK-SPIX)
RPIX
50%
50%
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 31 of 33
M65761FP (2) Through Input Mode
XRDY
50% tPLH (XTIM-XRDY)
XTIM
tsu (MCLK-XTIM)
MCLK
tPHL (MCLK-XCLK)
tPLH (MCLK-XCLK)
XWAIT tc (XCLK) tw- (XCLK) XCLK tw+ (XCLK) th (XCLK-XWAIT) th (XCLK-XTIM)
tsut (XCLK-CX0 to 11) tsut (XCLK-SPIX)
CX0 to 11 SPIX
tht (XCLK-CX0 to 11) tht (XCLK-SPIX)
tk (XCLK-PEUPE)
PEUPE
tPLH (XCLK-RPIX)
tPHL (XCLK-RPIX)
RPIX
50%
50%
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 32 of 33
M65761FP
Package Dimensions
JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JB-A Previous Code 100P6S-A MASS[Typ.] 1.6g
HD *1 80
D 51
81
50 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
ZE
Reference Symbol
Dimension in Millimeters
100
31
1
ZD
Index mark
30 F
c
L e y *3 bp Detail F
D E A2 HD HE A A1 bp c e y ZD ZE L
Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.25 0.3 0.4 0.13 0.15 0.2 0 10 0.5 0.65 0.8 0.10 0.575 0.825 0.4 0.6 0.8
A
REJ03F0234-0200 Rev.2.00 Sep 14, 2007 Page 33 of 33
A1
A2
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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